Fixed optimizer bug where certain syscalls were not included in register liveness analysis

rust_compiler/libs/integration_tests/src/lib.rs

@@ -18,6 +18,12 @@ mod tests {
         let compiler = Compiler::new(parser, None);
         let result = compiler.compile();
 
+        assert!(
+            result.errors.is_empty(),
+            "Compilation errors: {:?}",
+            result.errors
+        );
+
         // Get unoptimized output
         let mut unoptimized_writer = std::io::BufWriter::new(Vec::new());
         result
@@ -219,4 +225,20 @@ mod tests {
         let output = compile_with_and_without_optimization(source);
         insta::assert_snapshot!(output);
     }
+
+    #[test]
+    fn test_setbatched_with_member_access() {
+        let source = indoc! {r#"
+            const SENSOR = 20088;
+            const PANELS = hash("StructureSolarPanelDual");
+            
+            loop {
+              setBatched(PANELS, "Horizontal", SENSOR.Horizontal);
+              setBatched(PANELS, "Vertical", SENSOR.Vertical + 90);
+              yield();
+            }
+        "#};
+        let output = compile_with_and_without_optimization(source);
+        insta::assert_snapshot!(output);
+    }
 }

rust_compiler/libs/integration_tests/src/snapshots/integration_tests__tests__setbatched_with_member_access.snap

@@ -0,0 +1,28 @@
+---
+source: libs/integration_tests/src/lib.rs
+assertion_line: 242
+expression: output
+---
+## Unoptimized Output
+
+j main
+main:
+__internal_L1:
+l r1 20088 Horizontal
+sb -539224550 Horizontal r1
+l r2 20088 Vertical
+add r3 r2 90
+sb -539224550 Vertical r3
+yield
+j __internal_L1
+__internal_L2:
+
+## Optimized Output
+
+l r1 20088 Horizontal
+sb -539224550 Horizontal r1
+l r2 20088 Vertical
+add r3 r2 90
+sb -539224550 Vertical r3
+yield
+j 0